Back end of line (BEOL) interconnect structures have been developed that complement the progressive scaling of the feature sizes and critical dimensions of semiconductor devices and integrated circuits. In a typical multilevel interconnect structure, two or more separate levels of conductive lines extend laterally across a substrate carrying the integrated circuit. Insulating layers of dielectric material separate and electrically isolate conductive lines in adjacent levels. Conductive contacts extend through vias in the insulating layers to connect conductive lines in adjacent levels.
The conductive lines and contacts of the BEOL interconnect structure cooperate to distribute signals among the devices and integrated circuits on the substrate. The conductive lines of the first metallization, which are in the initial level of the interconnect structure nearest to the substrate, primarily interconnect the devices of the integrated circuit and may optionally provide circuit-to-circuit connections. The conductive lines in the upper levels of the interconnect structure complete the circuit-to-circuit connections and establish contacts with input and output terminals. Despite advanced designs that more effectively route signal paths of the integrated circuit, the signal-transmission effectiveness and efficiency of the interconnect structure may eventually limit the ultimate performance of the integrated circuit.
BEOL interconnect structures exhibit an intrinsic signal propagation delay dependent upon the resistance of the interconnect lines and contacts and also upon the capacitance of the dielectric materials in which the conductive lines and contacts are embedded. Forming conductive lines and contacts from copper (Cu) has been found to reduce the resistance contribution to the signal propagation delay. The capacitance contribution to the signal propagation delay may be reduced by using low dielectric constant (low-k) dielectrics having a dielectric constant, k, of about 3.9 or less. As feature sizes and critical dimensions are scaled below 90 nm, the combination of copper metal and low-k dielectric materials has been demonstrated to minimize signal propagation delay particularly well.
Copper-dielectric BEOL interconnect structures are routinely fabricated by damascene processes. In single damascene processes, vias are selectively etched in a dielectric layer masked by a patterned resist. After the resist is stripped, metal is deposited to fill the vias and to establish contacts with underlying conductor lines or other conductive structures. Trenches are then etched in another patterned layer of dielectric material deposited on the initial dielectric layer and subsequently filled with deposited metal to define overlying conductive lines. The conductive lines in adjacent levels of the interconnect structure are electrically coupled by the contacts. Dual-damascene processes differ in that the trenches and vias are etched in one or more layers of insulating or dielectric material and then filled simultaneously by a single blanket deposition of metal. Repeating these damascene processes forms subsequent levels of the interconnect structure.
Conventional copper-dielectric BEOL interconnect structures include a conductive liner situated between the dielectric material and the conductive lines and contacts. In particular, the use of copper metal in interconnect manufacture requires an adhesion layer between the copper metal and the dielectric material to promote bonding and a diffusion barrier between the copper metal and the dielectric material to isolate the copper from the dielectric material. Liners, such as a bilayer of TaN/Ta, have proven to be effective for copper interconnects by isolating the conductive copper metal from the bordering low-k dielectric material as well as strongly bonding the copper metal and the dielectric material. The liner covers the bottom and sidewalls of the trench bearing the conductive line.
Migration of metals, such as copper, from conductive features of the BEOL interconnect structure into the nearby dielectric material may compromise the integrity of the insulating layers. In particular, metal contamination of the dielectric material may promote significant leakage currents among the interconnect levels. Furthermore, electromigration induced by electron flow during normal circuit operation may cause mass transport of the conductor in the interconnect structure in the direction of the electron flow and at a rate determined by the current density. The mass depletion arising from electromigration may eventually result in thinned conductive lines characterized by increased resistivity.
Electromigration may be reduced in BEOL interconnect structures that rely on aluminum metal for conductive lines and contacts by adding a small amount of an appropriate dopant to the aluminum metal. The electromigration of aluminum is recognized as occurring by a bulk transport mechanism that the presence of the dopant mitigates. On the other hand, the electromigration of copper is recognized to primarily occur by a surface transport mechanism, which cannot be satisfactorily mitigated by merely introducing a bulk dopant. As feature sizes and critical dimensions are scaled below 90 nm, the reliability of copper-based interconnect structures may be particularly prone to compromise by electromigration.
In conventional copper-based BEOL interconnect structures, the top surface of the conductive line is often covered by a dielectric capping layer, such as silicon nitride. Because electromigration occurs by a surface transport mechanism in copper-based interconnect structures, the resulting mass transport of copper primarily occurs at interfaces between copper and the contacting material, such as the interface between the conductive line and the dielectric capping layer. In the latter instance, the escaping copper diffuses or migrates along the interface between the dielectric capping layer and the underlying insulating layer of the interconnect level. As the distance between adjacent interconnect levels is reduced, the mobility of copper metal contamination along this interface significantly increases the risk of dielectric breakdown and leakage.
Conventional copper-based BEOL interconnect structures may also rely on metal capping layers applied to the top surface of the conductive line as a substitute for dielectric capping layers. Selective deposition techniques have been developed that are capable of forming metal capping layers on the top surface of the conductive lines, but not on the top surface of the surrounding dielectric material. However, even such selective deposition processes may leave unwanted metal residues on the insulating layer because the deposition selectivity is not perfect. Moreover, the selectively-deposited metal capping layer is only coextensive with the underlying conductive line, which leaves an open interface at the peripheral edge of the capping layer.
Metal contamination of the dielectric material in the insulating layer of the BEOL interconnect structure may also originate from artifacts of the damascene process. Specifically, damascene processes fill the trenches and vias with conductor originating from a blanket deposition of metal. A planarization process, such as chemical-mechanical polishing (CMP), removes excess metal covering the top surface of the insulating layer. After planarization, metal residues on the insulating layer represent another potential contamination source for the constituent dielectric material.
What is needed, therefore, are design structures with interconnect structures configured to reduce or eliminate the electromigration of the constituent conductive material, such as copper, from conductive features into the surrounding insulating layer.